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ds04-21373-1e fujitsu semiconductor data sheet assp dual s erial input pll frequency synthesizer mb15f76ul n description the fujitsu mb15f76ul is a serial input phase locked loop (pll) frequency synthesizer with a 6.0 ghz and a 1.5 ghz prescalers. both prescalers for rf and if have a 1/4 divider. a 16/17 or a 32/33 for the 6.0 ghz prescaler, and a 4/5 or a 8/9 for the 1.5 ghz prescaler can be selected for the prescaler that enables pulse swallow operation. the bicmos process is used, as a result a supply current is typically 8.5 ma at 3.0 v. the supply voltage range is from 2.5 v to 3.6 v. a refined charge pump supplies well-balanced output current with 1.5 ma and 6 ma selectable by serial date. the pin assignments are is the same as the mb15f78ul. fast locking is achieved for adopting the new circuit. the new package (bcc20) decreases a mount area of mb15f76ul more than 30 % comparing with the former bcc16 (for dual pll) . n pac k ag e 20-pad plastic bcc (lcc-20p-m05)
mb15f76ul 2 n features ? high frequency operation : rf synthesizer : 6.0 ghz max : if synthesizer : 1.5 ghz max ? low power supply voltage : v cc = 2.5 v to 3.6 v ? ultra low power supply current : i cc = 8.5 ma typ (v cc = vp = 3.0 v, ta = + 25 c, sw if = sw rf = 0 in if/rf locking state) ? direct power saving function : power supply current in power saving mode ty p. 0 . 1 m a (v cc = vp = 3.0 v, ta = + 25 c) max. 10 m a (v cc = vp = 3.0 v) ? software selectable charge pump current : 1.5 ma/6.0 ma typ ? dual modulus prescaler : 6.0 ghz prescaler (1/4 divider and 16/17 or 32/33) / 1.5 ghz prescaler (1/4 divider and 4/5 or 8/9) ? 23-bit shift register ? serial input binary 14-bit programmable reference divider : r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 5-bit swallow counter : 0 to 31 - binary 13-bit programmable counter : 3 to 8,191 ? built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit ? on-chip phase control for phase comparator ? on-chip phase comparator for fast lock and low noise ? built-in digital locking detector circuit to detect pll locking and unlocking ? operating temperature : ta = - 40 c to + 85 c n pin assignment (bcc-20) top view (lcc-20p-m05) fin if xfin if gnd if v ccif ps if vp if 1 2 3 4 5 6 16 15 14 13 12 11 le fin rf xfin rf gnd rf v ccrf ps rf 78910 20 19 18 17 do if do rf ld/fout vp rf gnd osc in data clock
mb15f76ul 3 n pin description pin no. pin name i/o descriptions 1fin if i prescaler input pin for the if-pll. connection to an external vco should be ac coupling. 2xfin if i prescaler complimentary input for the if-pll section. this pin should be grounded via a capacitor. 3gnd if ? ground pin for the if-pll section. 4v ccif ? power supply voltage input pin for the if-pll section (except for the charge pump circuit), the shift register and the oscillator input buffer. 5ps if i power saving mode control pin for the if-pll section. this pin must be set at l when the power supply is started up. (open is prohibited.) ps if = h ; normal mode/ps if = l ; power saving mode 6vp if ? power supply voltage input pin for the if-pll charge pump. 7do if o charge pump output for the if-pll section. 8 ld/fout o lock detect signal output (ld) /phase comparator monitoring output (fout) pin. the out- put signal is selected by lds bit in a serial data. lds bit = h ; outputs fout signal/lds bit = l ; outputs ld signal 9do rf o charge pump output for the rf-pll section. 10 vp rf ? power supply voltage input pin for the rf-pll charge pump. 11 ps rf i power saving mode control for the rf-pll section. this pin must be set at l when the power supply is started up. (open is prohibited. ) ps rf = h ; normal mode/ps rf = l ; power saving mode 12 v ccrf ? power supply voltage input pin for the rf-pll section (except for the charge pump cir- cuit) 13 gnd rf ? ground pin for the rf-pll section 14 xfin rf i prescaler complimentary input pin for the rf-pll section. this pin should be grounded via a capacitor. 15 fin rf i prescaler input pin for the rf-pll. connection to an external vco should be via ac coupling. 16 le i load enable signal input pin (with the schmitt trigger circuit) when le is set h, data in the shift register is transferred to the corresponding latch ac- cording to the control bit in a serial data. 17 data i serial data input pin (with the schmitt trigger circuit) data is transferred to the corresponding latch (if-ref. counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in a serial data. 18 clock i clock input pin for the 23-bit shift register (with the schmitt trigger circuit) one bit data is shifted into the shift register on a rising edge of the clock. 19 osc in i the programmable reference divider input pin. tcxo should be connected with an ac coupling capacitor. 20 gnd ? ground pin for osc input buffer and the shift register circuit.
mb15f76ul 4 n block diagram clock data le ps rf xfin rf fin rf osc in fin if ps if v ccif gnd if fp if do if ld if t1 t2 t1 t2 fc rf sw rf lds do rf or ld / fout ld fr if fr rf fp if fp rf fr if fr rf fp rf c n 1 c n 2 and v ccrf gnd rf vp rf 4 3 7 8 9 13 10 gnd 12 18 17 16 11 14 15 19 1 xfin if 2 5 vp if 6 intermittent mode control (if-pll) modulus (4/5, 8/9) 5 bit latch 13 bit latch binary 5-bit swallow counter (if-pll) binary 13-bit programmable counter (if-pll) phase comp. (if-pll) charge pump (if-pll) current switch 2 bit latch 14 bit latch 1 bit latch binary 14-bit pro- grammable ref. counter(if-pll) c/p setting counter lock det. (if-pll) 2 bit latch 14 bit latch 1 bit latch binary 14-bit pro- grammable ref. counter (rf-pll)) c/p setting counter selector modulus (16/17, 32/33) lock det. (rf-pll) intermittent mode control (rf-pll) 3 bit latch fc if sw if lds 3 bit latch 5 bit latch 13 bit latch binary 5-bit swallow counter (rf-pll) binary 13-bit programmable counter (rf-pll) phase comp. (rf-pll) fast lock tuning charge pump (rf-pll) current switch schmitt circuit latch selector schmitt circuit schmitt circuit 23-bit shift register fast lock tuning ld rf fp rf 20 prescaler (if-pll) 1/4 divider prescaler (rf-pll) 1/4 divider fast lock tuning
mb15f76ul 5 n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions note : v ccrf , vp rf , v ccif and vp if must supply equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to v ccrf , vp rf , v ccif and vp if to keep them equal. it is recommended that the non-use pll is controlled by power saving function. although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the following precautions when handling the device. when storing and transporting the device, put it in a conductive case. before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. use a conductive sheet on working bench. before fitting the device into or removing it from the socket, turn the power supply off. when handling (such as transporting) the device mounted board, protect the leads with a conductive sheet. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. power supply voltage v cc - 0.5 4.0 v vp v cc 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld/fout v o gnd v cc v do if , do rf v do gnd vp v storage temperature tstg - 55 + 125 c parameter symbol value unit remarks min. typ. max. power supply voltage v cc 2.5 3.0 3.6 v v ccrf = v ccif vp v cc 3.0 3.6 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15f76ul 6 * n electrical characteristics (v cc = 2.5 v to 3.6 v, ta = - 40 c to + 85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current i ccif *1 fin if = 570 mhz, v ccif = vp if = 3.0 v 1.8 2.3 2.9 ma i ccrf *1 fin rf = 4750 mhz, v ccrf = vp rf = 3.0 v 5.2 6.2 7.5 ma power saving current i psif ps if = ps rf = l ? 0.1 *2 10 m a i psrf ps if = ps rf = l ? 0.1 *2 10 m a operating frequency fin if *3 fin if if pll 100 ? 1500 mhz fin rf *3 fin rf rf pll 2000 ? 6000 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin if pfin if if pll, 50 w system - 15 ?+ 2dbm fin rf pfin rf rf pll, 50 w system - 10 ?+ 2dbm input available voltage osc in v osc ? 0.5 ? v cc v p - p h level input voltage data le clock v ih schmitt trigger input 0.7 v cc + 0.4 ?? v l level input voltage v il schmitt trigger input ?? 0.3 v cc - 0.4 v h level input voltage ps if ps rf v ih ? 0.7 v cc ?? v l level input voltage v il ??? 0.3 v cc v h level input current data le clock ps i ih *4 ?- 1.0 ?+ 1.0 m a l level input current i il *4 ?- 1.0 ?+ 1.0 m a h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il *4 ? - 100 ? 0 m a h level output voltage ld/ fout v oh v cc = vp = 3.0 v, i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = vp = 3.0 v, i ol = 1 ma ?? 0.4 v h level output voltage do if do rf v doh v cc = vp = 3.0 v, i doh = - 0.5 ma vp - 0.4 ?? v l level output voltage v dol v cc = vp = 3.0 v, i dol = 0.5 ma ?? 0.4 v high impedance cutoff current do if do rf i off v cc = vp = 3.0 v v off = 0.5 v to vp - 0.5 v ?? 2.5 na h level output current ld/ fout i oh *4 v cc = vp = 3.0 v ??- 1.0 ma l level output current i ol v cc = vp = 3.0 v 1.0 ?? ma
mb15f76ul 7 (continued) (v cc = 2.5 v to 3.6 v, ta = - 40 c to + 85 c) *1 : conditions ; fosc = 10.0 mhz, ta = + 25 c, sw = l in locking state. *2 : v ccif = vp if = v ccrf = vp rf = 3.0 v, fosc = 10.0 mhz, ta = + 25 c, in power saving mode. ps if = ps rf = gnd v ih = v cc , v il = gnd (at clk, data, le) *3 : ac coupling. 1000 pf capacitor is connected under the condition of min. operating frequency. *4 : the symbol C (minus) means the direction of current flow. *5 : v cc = vp = 3.0 v, ta = + 25 c (||i 3 | - |i 4 ||) / [ (|i 3 | + |i 4 |) / 2] 100 ( % ) *6 : v cc = vp = 3.0 v, ta = + 25 c [ (||i 2 | - |i 1 ||) / 2] / [ (|i 1 | + |i 2 |) / 2] 100 ( % ) (applied to both l dol and l doh ) *7 : v cc = vp = 3.0 v, [||i do ( + 85 c ) | - |i do ( C40 c ) || / 2] / [|i do ( + 85 c ) | + |i do ( C40 c ) | / 2] 100 ( % ) (applied to both i dol and i doh ) *8 : when charge pump current is measured, set lds = l , t1 = l and t2 = h. parameter symbol condition value unit min. typ. max. h level output current do if *8 do rf i doh *4 v cc = vp = 3.0 v, v doh = vp / 2, ta = + 25 c cs bit = h - 8.2 - 6.0 - 4.1 ma cs bit = l - 2.2 - 1.5 - 0.8 ma l level output current do if *8 do rf i dol v cc = vp = 3.0 v, v dol = vp / 2, ta = + 25 c cs bit = h 4.1 6.0 8.2 ma cs bit = l 0.8 1.5 2.2 ma charge pump current rate i dol /i doh i domt *5 v do = vp / 2 ? 310 % vs v do i dovd *6 0.5 v v do vp - 0.5 v ? 10 15 % vs ta i dota *7 - 40 c ta + 85 c, v do = vp / 2 ? 510 % i dol i 1 i 3 i 2 i 1 i 4 i 2 0.5 vp/2 vp - 0.5 vp i doh charge pump output voltage (v)
mb15f76ul 8 n functional description 1. pulse swallow function f vco = [ (p n) + a] 4 f osc ? r f vco : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of dual modulus prescaler (4 or 8 for if-pll, 16 or 32 for rf-pll) n : preset divide ratio of binary 13-bit programmable counter (3 to 8,191) a : preset divide ratio of binary 5-bit swallow counter (0 a 31, a < n) f osc : reference oscillation frequency (osc in input frequency) r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. serial data input the serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf- pll sections, programmable reference dividers of if/rf-pll sections are controlled individually. the serial data of binary data is entered through data pin. on rising edge of clock, one bit of the serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. (1) shift register configuration the programmable reference counter for the if-pll the programmable reference counter for the rf-pll the programmable counter and the swallow counter for the if-pll the programmable counter and the swallow counter for the rf-pll cn1 0 1 0 1 cn2 0 0 1 1 ? programmable reference counter cs : charge pump current select bit r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383) t1, 2 : ld/fout output setting bit cn1, 2 : control bit x : dummy bits (set 0 or 1) note : data input with msb first. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cn1 cn2 t1 t2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 cs x x x x (lsb) (msb) data flow
mb15f76ul 9 (2) data setting ? binary 14 - bit programmable reference counter data setting note : divide ratio less than 3 is prohibited. ? binary 13 - bit programmable counter data setting note : divide ratio less than 3 is prohibited ? binary 5 - bit swallow counter data setting divide ratio r14r13r12r11r10r9r8r7r6r5r4r3r2r1 3 00000000000011 4 16383 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ration13n12n11n10n9n8n7n6n5n4n3n2n1 3 0000000000011 4 8191 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratioa5a4a3a2a1 0 00000 1 31 0 1 0 1 0 1 0 1 1 1 ? programmable counter a1 to a5 : divide ratio setting bits for the swallow counter (0 to 31) n1 to n13 : divide ratio setting bits for the programmable counter (3 to 8,191) lds : ld/fout signal select bit sw if / rf : divide ratio setting bit for the prescaler (if : sw if , rf : sw rf ) fc if / rf : phase control bit for the phase detector (if : fc if , rf : fc rf ) cn1, 2 : control bit note : data input with msb first. 1 2 3 4 5 6 7 8 9 10111213141516171819 20 21 22 23 cn1 cn2 lds sw if / rf fc if / rf a1 a2 a3 a4 a5 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 (lsb) (msb) data flow
mb15f76ul 10 ? prescaler data setting ? charge pump current setting ? ld / fout output selectable bit setting ? phase comparator phase switching data setting z : high-impedance depending upon the vco and lpf polarity, fc bit should be set. divide ratio sw = = = = h sw = = = = l prescaler divide ratio if-pll 4/5 8/9 prescaler divide ratio rf-pll 16/17 32/33 current value cs 6.0 ma 1 1.5 ma 0 ld/fout pin state lds t1 t2 ld output 000 010 011 fout output fr if 100 fr rf 110 fp if 101 fp rf 111 phase comparator input fc if , rf = = = = h fc if , rf = = = = l do if , rf do if , rf fr > fp h l fr < fp l h fr = fp z z (1) (2) (1) vco polarity fc = h (2) vco polarity fc = l note : give attention to the polarity for using active type lpf. vco output frequency high lpf output voltage max.
mb15f76ul 11 3. power saving mode (intermittent mode control circuit) the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes : when power (vcc) is first applied, the device must be in standby mode. ps pin must be set l at power-on. status ps pin normal mode h power saving mode l on off v cc clock data le ps (1) (2) (3) t ps 3 100 ns t v 3 1 m s (1) ps = l (power saving mode) at power-on (2) set serial data at least 1 m s after the power supply becomes stable (v cc 3 2.2 v) . (3) release power saving mode (ps if , ps rf : l ? h) at least 100 ns later after setting serial data.
mb15f76ul 12 4. serial data input timing divide ratio is performed through a serial interface using the data pin, clock pin, and le pin. setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the le signal. the following diagram shows the data input timing. lsb msb clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 1st data 2nd data control bit invalid data note : le should be l when the data is transferred into the shift register. parameter min typ max unit parameter min typ max unit t 1 20 ?? ns t 5 100 ?? ns t 2 20 ?? ns t 6 20 ?? ns t 3 30 ?? ns t 7 100 ?? ns t 4 30 ?? ns
mb15f76ul 13 n phase comparator output waveform ? ld output logic notes : phase error detection range = - 2 p to + 2 p pulses on do if/rf signals during locking state are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu 3 2/fosc : e.g. t wu 3 200 ns when fosc = 10.0 mhz t wu 4/fosc : e.g. t wl 400 ns when fosc = 10.0 mhz if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l fr if / rf fp if / rf ld d o if / rf t wu t wl d o if / rf h l l h z z (fc bit = high) ( fc bit = low )
mb15f76ul 14 n test circuit (for measuring input sensitivity fin/osc in ) mb15f76ul 1 2 3 4 5 6 78 91011 12 13 14 15 16 17 18 19 20 gnd osc in clock data le fin rf xfin rf gnd rf v ccrf ps rf vprf d orf ld/fout do if oscilloscope vp if vp if ps if v ccif gnd if xfin if finif vprf v ccif 0.1 m f 0.1 m f 0.1 m f 0.1 m f v ccrf 1000 pf 1000 pf 1000 pf 1000 pf 1000 pf s.g s.g s.g 50 w 50 w 50 w controller (divide ratio setting)
mb15f76ul 15 n typical characteristics 1. fin input sensitivity 10 0 -30 -40 -50 -10 -20 0 1000 2000 3000 4000 5000 6000 7000 fin rf [mhz] pfin rf [dbm] v cc = 2.5 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec spec v cc = 2.5 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec 10 0 -10 -20 -30 -40 -50 0 500 1000 1500 2000 2500 3000 3500 4000 fin if [mhz] pfin if [dbm] spec rf-pll input sensitivity vs. input frequency if-pll input sensitivity vs. input frequency
mb15f76ul 16 2. osc in input sensitivity v cc = 2.5 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec spec 10 0 -10 -20 -30 -40 -50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 input sensitivity vs. input frequency input frequency f osc (mhz) input sensitivity v osc (dbm)
mb15f76ul 17 3. rf-pll do output current ? 1.5 ma mode ? 6.0 ma mode v cc = vp = 3.0 v 10.0 0 - 10.0 0.0 1.0 2.0 3.0 charge pump output current i do (ma) i do - v do charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) v cc = vp = 3.0 v 10.0 0 - 10.0 1.0 3.0 0.0 2.0
mb15f76ul 18 4. if-pll do output current ? 1.5 ma mode ? 6.0 ma mode i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) 10.0 0 - 10.0 1.0 3.0 v cc = vp = 3.0 v 0.0 2.0 i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) v cc = vp = 3.0 v 10.0 0 - 10.0 1.0 3.0 0.0 2.0
mb15f76ul 19 5. fin input impedance 1 2 3 4 -92.027 w 1.153 pf 1 500. 000 000 mhz 3 : 30.18 w -155.06 w 1 ghz start 100. 000 000 mhz stop 1 500. 000 000 mhz 4 : 20.141 w 1 : 714.75 w -1.2319 k w 100 mhz 2 : 64.484 w -318.44 w 500 mhz 1 2 3 4 4 : 22.418 w 67.184 w 6 000. 000 000 mhz 1 : 19.186 w -63.068 w 2 ghz 2 : 18.665 w -14.222 w 3 ghz 3 : 21.018 w 29.733 w 5 ghz start 2 000. 000 000 mhz stop 6 000. 000 000 mhz fin if input impedance fin rf input impedance
mb15f76ul 20 6. osc in input impedance osc in input impedance 4 : 064.94 w -1.0402 k w 1.5301 pf 100. 000 000 mhz 1 : 19.527 k w -13.395 k w 3 mhz 2 : 4.5245 k w -8.9645 w 10 mhz 3 : 305.63 w -2.6423 k w 40 mhz start 3. 000 000 mhz stop 100. 000 000 mhz 1 2 3 4
mb15f76ul 21 n reference information ( for phase noise and reference leakage ) test circuit s.g. osc in fin do lpf vco spectrum analyzer 910 w 3.9 k w 8200 pf 820 pf 470 pf f vco = 4750 mhz v cc = 3.0 v ta = + 25 c fr = 250 khz (channel spacing = 1 mhz) f osc = 13 mhz cp : 1.5 ma mode lpf to vco ? pll reference leakage ? pll phase noise atten 10db rl 0 dbm vavg 16 10 db/ d mkr -74.00 db 1.000 mhz d s center 4.750000 ghz *rbw 30 khz vbw 30 khz span 5.000 mhz *swp 2.00 s d mkr 1.000 mhz -74.00 db reference leak : -74.00 dbc atten 10 db rl 0 dbm vavg 16 10 db/ d mkr -72.17 db/hz 1.00 khz center 4.75000000 ghz *rbw 30 hz vbw 30 hz span 10.00 khz swp 1.92 s c/n d 1 khz : -72.17 dbc/hz d s atten 10 db rl 0 dbm vavg 16 10 db/ d mkr -69.62 db/hz 17.5 khz d s center 4.7500000 ghz *rbw 300 hz vbw 300hz span 100.0khz *swp 3.00 s c/n peak : -69.62 dbc/hz bw : 33.5 khz d mkr 1.00 khz -72.17 db/hz d mkr 17.5 khz -69.62 db/hz
mb15f76ul 22 n application example 1 2 3 4 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 mb15f76ul tcxo 1000 pf from controller 1000 pf 1000 pf 3.0 v 0.1 m f 3.0 v 0.1 m f 0.1 m f 0.1 m f 3.0 v 3.0 v 1000 pf lpf vco lpf vco output output gnd osc in clock data lock det. le fin rf xfin rf gnd rf v ccrf ps rf do if ld/fout do rf vp rf fin if xfin if gnd if v ccif ps if vp if 1000 pf notes : clock, data, le : the schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) .
mb15f76ul 23 n usage precautions (1) v ccrf , vp rf , v ccif and vp if must be equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to v ccrf , vp rf , v ccif and vp if to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions : store and transport devices in conductive containers. use properly grounded workstations, tools, and equipment. turn off power before inserting or removing this device into or from a socket. protect leads with conductive sheet, when transporting a board mounted device n ordering information part number package remarks MB15F76ULPVA 20-pad plastic bcc (lcc-20p-m05)
mb15f76ul 24 n package dimensions 20-pad plastic bcc (lcc-20p-m05) dimensions in mm ( inches ) c 2001 fujitsu limited c20056s-c-2-1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.55?.05 0.075?.025 (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) (.003?001) (mounting height) (.022?002)
mb15f76ul fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0209 ? fujitsu limited printed in japan

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